VHDL and ALTERA
QUARTUS II Courses
Via Rocca di Papa, 21 –00179 Roma, Italy
Email: info@geb-enterprise.com - Web: www.geb-enterprise.com

La GEB Enterprise S.r.l., ACAP certified partner of Altera, a leading company in
FPGA market, and AAP certified partner of JTAG Technologies, organizes courses
VHDL for FPGA VHDL design, for System On Programmable Chip (SOPC), for
BSCAN DFT (Design For Test , BSCAN oriented), for JTAG test operators.
The courses range from the VHDL language, with source level simulation in a
vendor independent platform (Aldec Active HDL and / or Model Sim) to the codingoriented synthesis. The methodologies of synthesis and optimization are focused on
Altera Quartus II platform. GEB organizes training courses that make the attendees
able to design systems on programmable chip (SOPC) with a 32 Bits multiprocessor
architectures, 32Bit NiosII embedded CPU, integrated into the Altera SOPC and
IDE, with peripherals and custom instructions to increase system performance.
The courses can take place in specific GEB partner’s classrooms or at the Customer premises. All courses are
confirmed when a minimum of n°4 attendees is achieved. More sessions are organized for a number of
attendees exceeding n°10. Attendees will receive electronic and/or printed versions of the course materials:
photocopies of slides, practical examples, CD with the exercises. At the end of the course a certificate of
participation is issued. The course fee may include an "educational board" to continue, extend and repeat the
exercises afterwords, at the Customer premises.

VEC100-Introduction to VHDL
This two-day course is a general introduction to the VHDL language and its use in programmable logic design.
The emphasis is on the synthesis constructs of VHDL; however, you will also learn about the simulation
constructs. You will gain a basic understanding of VHDL to enable you to begin creating your design file. In the
hands-on laboratory sessions, you will put this knowledge to the test by writing simple but practical designs.
You will also learn the basic instructions needed for operating both the synthesis and simulation tools of the
Quartus® II software.

VEC101-Advanced VHDL Design Techniques
In this course, you will learn & practice efficient coding techniques for VHDL
synthesis. You will gain experience writing behavioral & structural code & learn to
effectively code common logic functions including registers, memory & arithmetic
functions. You will use VHDL constructs to parameterize your designs to increase
their flexibility and reusability. While the concepts presented will mainly be
targeting Altera® devices using the Quartus® II software environment, many can
be applied to synthesizing hardware using other synthesis tools as well. You will
also be introduced to testbenches, VHDL constructs used to build them & common
ways to write them. The hands-on exercises will use Quartus II software to process
VHDL code and ModelSim®-Altera software for simulation.

VEC102VEC102-QUARTUS II: Foundation
You will learn how to use the Quartus® II software to develop an FPGA or CPLD. You
will create a new project, enter in new or existing design files, and compile your
design. You will also learn about timing constraints and analyze a design compiled with
these constraints using the TimeQuest timing analyzer, the path-based static timing
analysis tool included with the Quartus II software. You will learn techniques to help
you plan your design. You will employ Quartus II features that can help you achieve
design goals faster. You will also learn how to plan and manage I/O assignments for
your target device.

VEC107-QUARTUS II: Timing Analysis
You will learn how to constrain & analyze a design for timing using the TimeQuest timing analyzer in the
Quartus® II software. This includes understanding FPGA timing parameters, writing Synopsys Design
Constraint (SDC) files, generating various timing reports in the TimeQuest timing analyzer & applying this
knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets
timing, you will see how the TimeQuest timing analyzer makes it easy to create timing constraints to help you
meet those requirements.

VEC103-QUARTUS II: Verification & Optimization
You will learn features of the Quartus® II software that will enable you to verify your FPGA design and will
enable you to shorten your design cycle as well as improve your design performance and utilization.
Verification: You will learn how to simulate Altera IP and megafunctions in other EDA simulation tools. You will