SY10/100E445 4-Bit Serial-to-Parallel Converter0 pages

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SY10E445
Micrel, Inc. SY100E445
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
Pin Function
SINA, SINA Differential Serial Data Input A
SINB, SINB Differential Serial Data Input B
SEL Serial Input Select Pin
SOUT, SOUT Differential Serial Data Output
Q0–Q3 Parallel Data Outputs
CLK, CLK Differential Clock Inputs
CL/4, CL/4 Differential ÷4 Clock Output
CL/8, CL/8 Differential ÷8 Clock Output
MODE Conversion Mode 4-bit/8-bit
SYNC Conversion Synchronizing Input
RESET Input, Resets the Counters
VCCO VCC to Output
FEATURES DESCRIPTION
On-chip clock ÷4 and ÷8
Extended 100E VEE range of –4.2V to –5.5V
2.5Gb/s data rate capability
Differential clock and serial inputs
VBB output for single-ended use
Asynchronous data synchronization
Mode select to expand to 8 bits
Internal 75kÙ input pull-down resistors
Fully compatible with Motorola MC10E/100E445
Available in 28-pin PLCC package
4-BIT SERIAL-to-PARALLEL
CONVERTER
The SY10/100E445 are integrated 4-bit serial-to-parallel
data converters. The devices are designed to operate for
NRZ data rates of up to 2.5Gb/s. The chip generates a
divide-by-4 and a divide-by-8 clock for both 4-bit conversion
and a two-chip 8-bit conversion function. The conversion
sequence was chosen to convert the first serial bit to Q0,
the second to Q1, etc.
Two selectable serial inputs provide a loopback capability
for testing purposes when the device is used in conjunction
with the E446 parallel-to-serial converter.
The start bit for conversion can be moved using the
SYNC input. A single pulse, applied asynchronously for at
least two input clock cycles, shifts the start bit for conversion
from Qn to Qn-1 by one bit. For each additional shift required,
an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers
to "swallow" a clock pulse, effectively shifting a bit from the
Qn to the Qn-1 output (see Timing Diagram B).
The MODE input is used to select the conversion mode
of the device. With the MODE input LOW (or open) the
device will function as a 4-bit converter. When the mode
input is driven HIGH, the data on the output will change on
every eighth clock cycle, thus allowing for an 8-bit conversion
scheme using two E445s. When cascaded in an 8-bit
conversion scheme, the devices will not operate at the
2.5Gb/s data rate of a single device. Refer to the applications
section of this data sheet for more information on cascading
the E445.
For lower data rate applications, a VBB reference voltage
is supplied for single-ended inputs. When operating at clock
rates above 500MHz, differential input signals are
recommended. For single-ended inputs, the VBB pin is tied
to the inverting differential input and bypassed via a 0.01ìF
capacitor. The VBB provides the switching reference for the
input differential amplifier. The VBB can also be used to AC
couple an input signal.
SY10E445
SY100E445
PIN NAMES
Rev.: F Amendment: /0
Issue Date: March 2006