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AD9993: Integrated Mixed-Signal Front End (MxFE) Data Sheet0 pages
Integrated Mixed-Signal Front End (MxFE)
AD9993
Data Sheet
FEATURES
GENERAL DESCRIPTION
Quad 14-bit 250 MSPS ADC
SFDR = 83 dBc at 87 MHz input
Dual 14-bit 500 MSPS DAC
SFDR = 75 dBc at 20 MHz output
On-chip PLL clock synthesizer
Low power
1536 mW, 1 GHz master clock, on-chip synthesizer
500 MHz double data rate (DDR)
LVDS interfaces for DACs and ADCs
Small 12 mm × 12 mm lead-free BGA package
The AD9993 is a mixed-signal front-end (MxFE®) device that
integrates four 14-bit ADCs and two 14-bit DACs. Figure 1
shows the block diagram of the MxFE. The MxFE is
programmable using registers accessed via a serial peripheral
interface (SPI). ADC and DAC datapaths include FIFO buffers
to absorb phase differences between LVDS lane clocks and the
data converter sampling clocks.
APPLICATIONS
The MxFE DACs are part of the Analog Devices, Inc., high
speed CMOS DAC core family. These DACs are designed to be
used in wide bandwidth communication system transmitter
(Tx) signal chains.
Point to point microwave backhaul radios
Wireless repeaters
The MxFE ADCs are multistage pipelined CMOS ADC cores
designed for use in communications receivers.
FUNCTIONAL BLOCK DIAGRAM
2
14
DOUT3A_x TO DOUT0A_x
14
ADC_A
DOUT3B_x TO DOUT0B_x
4
2
14
DCO CLOCK
ADC_B
DOUT3C_x TO DOUT0C_x
LVDS
BUFFER
DOUT3D_x TO DOUT0D_x
DCO_x
STROBE
2
14
ADC_C
DIGITAL
ADC_D
–ADC AND DAC
DATAPATHS
–CONTROLS
–SPI REGISTERS
–FIFO BUFFERS
STROBE_x
2
14
2
14
DIN6A_x TO DIN0A_x
LVDS
BUFFER
DIN6B_x TO DIN0B_x
DCI CLOCK
DCI_x
14
DAC_A
4
SPI_SCLK, SPI_CS, SPI_SDI, SPI_SDO
RST
2
14
ALERT
PLL
0
1
250MHz
500MHz
CLOCK GENERATOR
DIV
MxFE
AD9993
12260-001
31.25MHz
OR
62.5MHz
250MHz
500MHz
DAC_B
1GHz
Figure 1.
Rev. A
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