TAP Checker - Product Information0 pages
TAP Checker™
Product Information
Automated testbench generator for IEEE 1149.x ICs
Full validation of Boundary Scan designs
Extended functionality for multichip modules and 3D chips
Compliant with all standard simulators
Test pattern export to chip test systems in production
Available for Windows, Oracle Solaris and Linux
Boundary Scan (IEEE Std. 1149.x) is a revolutionary technology substituting physical
access via nails and probes by means of special on-chip electronics (electronic nails)
in conjunction with a dedicated four-wire bus. TAP Checker is a powerful EDA tool to
validate such structures. Both the virtual verication based on functional simulations,
and the physical test of the silicon by respective chip test systems are supported.
TAP Checker can be utilised also for modern IC packages such as Multichip Modules
(MCM) or 3D chips.
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