MX.72xx - 16 bit Digital Pattern Generator with programmable logic levels0 pages

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MX.72xx - 16 bit Digital Pattern Generator with programmable logic levels
• PXI 3U / CompactPCI 3U format
• Programmable output levels from
-2,0 V up to +10,0 V
• Levels individually programmable per 4 bit
• Up to 40 MS/s at 16 bit
• Possible use of memory saving 8 bit mode
• All Outputs can be separately disabled (Tristate)
• Hardware controlled differential output possible (8 bit)
• Up to 128 MByte memory
• Output in FIFO mode
• Synchronization possible
Product range overview
Software/Drivers
A large number of drivers and examples are delivered
with the board or are available as an option:
• Windows 98/ME/NT/2000/XP/Vista/7 drivers
• Linux 32bit and 64bit drivers
• SBench 5.x for Windows
• Microsoft Visual C++ examples
• Borland Delphi examples
• Microsoft Visual Basic examples
• Microsoft Excel examples
• LabWindows/CVI examples
• FlexPro support with SBench
• LabVIEW - drivers (as option)
• DASYLab - drivers (as option)
• MATLAB - drivers (as option)
• Agilent VEE - drivers (as option)
General Information
The MX.72xx pattern generator series gives the user
the possibility to generate digital data with a wide
range of output levels. For every 4 bit the LOW and
HIGH levels can be programmed from -2.0 V up to
+10.0 V. Even at high speeds you are not limited concerning
the maximum output swing. This enables the
user to drive devices of nearly any logic family, like
ECL, PECL, TTL, LVDS, LVTTL, CMOS or LVCMOS. The
potentially necessary differential signals are generated
in hardware, so that only one data bit is used for
each pair of differential signals. All outputs can be seperately
disabled allowing the easy connection with
digital acquisition boards and the adaption to a wide
range of test setups. The internal standard synchronisation
bus allows synchronisation of several MX.xxxx
boards. Therefore the MX.72xx board can be used as
an enlargement to any digital or analog board.
Model 8 bit 16 bit
MX.7210 10 MS/s 10 MS/s
MX.7220 40 MS/s 40 MS/s
Hardware block diagram
Software programmable parameters
Application examples
sampling rate 1 kS/s to max sampling rate, external clock, ref clock, PXI clock
Output level LOW/HIGH level p. nibble;-2,0 V up to +10,0 V in steps of 1mV
Clock mode internal PLL, internal quartz, external, external divided, external
reference clock, PXI reference clock
Clock impedance 110 Ohm / 50 kOhm
Trigger impedance 110 Ohm / 50 kOhm
Data Enable mask programmable for every single bit
Trigger mode External TTL, software, PXI Line[5..0], PXI Startrigger
Memory depth 32 up to installed memory in steps of 32
Posttrigger 32 up to 128 M in steps of 32
Multiple Recording segmentsize 32 up to installed memory / 2 in steps of 32
Semiconductor test Production test Burn-in test
Laboratory purposes Pattern generator Semiconductor development
Process control ATE