TX4939XBG-400 64-bit RISC Processor0 pages

Product Brief
TX4939XBG-400 64-bit RISC
Processor
Highlights

Description

Features

• First 90 nm embedded

The TX4939 is the newest member of TX49
MIPS RISC microprocessor family. It is
ideally suited for low-power, highperformance applications like IP set-topboxes, home gateways and multimedia
appliances. The TX4939 microprocessor is a
highly integrated standard product based on
the Toshiba TX49/H4 400 MHz processor
core, a 64-bit MIPS I, II, III instruction set
architecture (ISA) compatible with additional
instructions.

• TX49/H4 core (on-chip IEEE754 compliant
single/double precision FPU)

The TX4939 has multiple on-chip peripheral
functions including 8/16-bit local bus
controller, a highly optimized security
engine, serial/parallel video ports, ATA
controllers, a DDR SDRAM controller, a
NAND flash controller, Ethernet MAC
controllers (RMII), a PCI controller, a DMA
controller, an interrupt controller, an AC-link
controller, serial and parallel ports,
timers/counters and real-time clock with
battery back-up support (RTC).

• Direct memory access controller (8 Channels
[4 Channels are dedicated to ACLC])

and FEC algorithms
• 32-bit DDR400 DRAM
controller
• High-power PCI controller
• 8/16-bit local bus for
NAND/NOR flash and
other I/O devices
• Two, 100 MB ATA/ATPI
channels
• Three serial or one serial

ITU Bt.656 standard
• On-chip Ethernet MAC
and NAND flash memory
controller

TX49/H4 CPU Core

• SPI (multiplexed with SIO ch2, ch3)
• 8-bit video port (SPI)
• Serial TS video port (Max 3-ports)
• Timer/counter (3 channels)
• AC-link controller / I2S (5.1ch) / I2S (2ch)

CP0 Register

GeneralPurpose
Register

DDR CLK

MMU/TLB
Pipeline
Control

Data Bus

DDR-SDRAM
Controller
32-Bits

Exception
Handling
Unit

FPU
32 KB
4-W.S.A.
Ins. Cache

SSCG
Modulator

SYS CLK

DMAC
8-ch

External Bus
Control
(NAND Flash)

32 KB
4-W.S.A.
Ins. Cache

support
• Built-in SSCG provides

UART0

SRAM
2 KB

the maximum EMI
reduction

PLL #3
Auto Clock
Test
JTAG
EJTAG

UART1
UART2
UART3

G-Bus 64-Bit 200 MHz
IMB

SPI
I 2C

PLL #1
400 MHz
PLL #2
800 MHz

RTC

Chain Mode

Clock Gen

with battery backup

Write
Buffer

Battery Back-up

DREQ/DACK

2-Chip
Selects
2-Banks
14-Address
Signals

CP1

MAC
Circuit
Debug
Support
Unit

External Bus
(16-Bit)

DDR IO
CP0

Integer Operation Unit

• Real time clock (RTC)

Descriptor
Drive
DMA
Engine

DES
3DES
AES
MD5
SHA1
RSA

www.Toshiba.com/taec

1

• SIO (4 channels, ch2 and ch3 are
multiplexed with synchronous parallel
interface (SPI)

TX4939 Block Diagram

and one 8-bit parallel
video ports compliant to

• PCI boot and satellite mode (PCI slave
mode) support

X32K, Bat.

implementing IPSec, SSL

F un ct i o n P i ns

loads CPU core for

• 32-bit PCI controller (33 MHz/66 MHz) with 4
clock outputs, arbiter and interrupts for 6
devices

TX4939XBG-400 64-bit RISC Processor

PCIC
No. 1

PCI 32-Bit
33/66 MHz

G-Bus
Bridge

ATA100
CH-0

EIDE

G-Bus
Bridge

8-Bit
Video
Port

Video

PGB No. 2

G-Bus
Bridge

IRC
(Interrupt)

PCIC No. 2

PGB No. 1

Timer
WDT
Control

Internal PCI 32-Bit/66 MHz
ATA100
CH-1

10/100
eMAC1

10/100
eMAC0

EIDE Interface or RMII

ACLINK
I 2S
(5.1ch &
2ch)

I 2C

security engine that off-

• 8/16-bit local bus for NAND/NOR flash and
other I/O devices

PI O o r
Fu nc t i on
P i ns

• High-performance

A C LI N K/ I 2 S

400 MHz TX49/H4 core

• DDR SDRAM controller
(2 channels: 32-bit/100-200MHz)

OSC
Regulator

processor product with

32-Bit IM Bus

PCI MIPS RISC