B4623B Bus Decoder for LPDDR, LPDDR2, or LPDDR3 Debug and Validation0 pages

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Agilent

B4623B Bus Decoder for

LPDDR, LPDDR2, or LPDDR3

Debug and Validation

Data Sheet

Physical Address

DDR Bus Decode

Deselect

Cycle Type

B4623B bus decode shown in listing

window—LPDDR2 example.

D29 5C00 Read CS-0 BA-3

Row Address = 0x34a5

Col Address = 0x100

Burst Type = Interleave

D29 5C00 mem read Ox------00

D29 5C04 mem read Ox------00

D29 5C08 mem read Ox------00

D29 5C0C mem read Ox------aa

D29 5C10 mem read Ox------55

D29 5C14 mem read Ox------cc

D29 5C18 mem read Ox------00

D29 5C1C mem read Ox------ff

Clock is disabled

Deselect

0000 0100

Idle

Description

Accelerate your time to insight using the B4623B bus decoder for LPDDR,

LPDDR2, or LPDDR3 debug and validation. The B4623B provides complete proto-

col decode of memory transactions using an Agilent logic analyzer as the analy-

sis execution engine. The B4623B protocol-decode software translates acquired

signals into easily understood bus transactions showing associated data bursts,

for all LPDDR, LPDDR2, or LPDDR3 data rates. Valid Read and Write commands

are decoded to include Row and Column Addresses and the complete data burst

associated with the command. The B4623B bus decode software anticipates key

system attribute inputs (Burst length, CAS Latency and CAS Write Latency, Chip

Selects) from default LPDDR, LPDDR2, or LPDDR3 probing configurations and/or

DDR Setup Assistant tool to accelerate decode of LPDDR, LPDDR2, or LPDDR3

bus signals.

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