Vitesse Service Aware Architecture (ViSAA)0 pages

CE Service Delivery

Vitesse Service Aware Architecture
The Challenge
As Enterprises and Carriers move increasingly to
cloud-based models, supporting carrier-class service
delivery in networking equipment becomes highly critical.
Today’s generic Ethernet switches are not service aware,
forcing OEMs to augment traditional switching silicon
with expensive external hardware components like FPGA,
NPUs, or both. It also often requires complex software
additions that impact performance, and ultimately, carrier
opex and revenue.
The Solution
Vitesse Service Aware Architecture (ViSAA™) technology
the industry’s only hardware-based service layer for
scalable, wirespeed performance and delivery of CE

services fully compliant with MEF CE 2.0. ViSAA is designed
for networking equipment, including Ethernet Access
Devices (EAD) and Network Interface Devices (NID), used for
small cell and macrocell backhaul in fiber and wireless
networks. When combined with Vitesse’s Intellisec™enabled PHYs, only ViSAA can enable the secure, high
performance and reliable networks required to move
mission-critical Enterprise applications to the cloud.
The Value of Choosing Vitesse
Vitesse technologies are engineered to meet converged
network needs for mobile access, wired and wireless
backhaul, and cloud access. Contact your local Vitesse sales
office to leverage our expertise to your advantage.

PART NO.

DESCRIPTION

KEY VITESSE FEATURES

VSC7416 Serval™ Lite

MPLS/MPLS-TP support, VeriTime IEEE1588v2 single-step timing with
transparent clock support, Y.1731, Y.156sam and low power
MPLS/MPLS-TP support, VeriTime IEEE1588v2 single-step timing with
transparent clock support, Y.1731, Y.156sam and low power

VSC7438 Serval-2™

6-Port Gigabit Ethernet CE
Switch Engine
11-Port Gigabit Ethernet CE
Switch Engine
11-Port Gigabit Ethernet CE Switch
Engine with Cu PHY
26-Port Gigabit Ethernet CE Switch
Engine with Cu PHY
32 Gbps CE Switch Engine

VSC7460 Jaguar-1™

4 x 10GE + 24 x GE CE Switch Engine

VeriTime IEEE1588v2 single-step timing with transparent clock support,
integrated Cu PHY
VeriTime IEEE1588v2 single-step timing with transparent clock support,
integrated Cu PHY
MPLS/MPLS-TP support, VeriTime IEEE1588v2 single-step timing with
transparent clock support, Y.1731, Y.156sam and ViSAA
MEF service aware architecture, low power

VSC7462 LynX-1™

2 x 10GE + 12 x GE CE Switch Engine

MEF service aware architecture, low power

VSC7418 Serval
VSC7428 Caracal-1™
VSC7429 Caracal-2™

www.vitesse.com/ce
© 2013 Vitesse Semiconductor Corporation. All rights reserved. All information in this document is subject to change without notice at any time
and Vitesse assumes no responsibility for use of any information herein. ViSSA Rev. 051613